Matrix display devices that can freely display text and images are being brought into practical use. These matrix display devices are made up of pixel units which are arranged in a matrix and have separate controls for light emission and light transmittance. Liquid crystal display panels and organic electroluminescence (EL) display panels are examples of matrix display devices.
Most matrix display devices are configured using an active-matrix substrate in which an active circuit for controlling light emission and light transmission is formed in of each of the pixel units. The active-matrix substrate is also referred to as a thin film transistor (TFT) array substrate.
Recently, there has been a remarkable increase in the pixel units provided in a matrix display device (hereafter referred simply as display device), and, with the increase in pixel units, the number of data lines provided for supplying luminance information to the respective pixel units has become enormous. Testing all the data lines is vital to guaranteeing the quality of the display device. However, connecting all the data lines simultaneously to a testing device is not realistic because the same enormous number as that for the data lines is required for the connections (for example, contact points of a prober) between the display device and the testing device.
A technique which defines a block for every predetermined number of data lines, sequentially selects one data line from each of the blocks, and performs testing using the selected data line is commonly known. According to this technique, it is possible to reduce the number of connections between the data lines and the testing device, and, in addition, sequentially perform testing using all of the data lines. An example of a liquid crystal device based on this technique is described in Patent Literature (PTL) 1.
FIG. 15 is a block diagram showing an electrical configuration of a liquid crystal device 900 in PTL 1.
The liquid crystal device 900 is configured of plural pixel units 901 that are arranged in a matrix on a TFT array substrate 908, and pixel units 901 are connected in common in each column of the matrix by a data line 902. One block is defined for every four adjacent data lines 902, and one terminal 903 is provided for each of the blocks.
At the time of testing, a test control circuit (not shown in the figure) supplies a predetermined data signal to the terminals 903 via a probe. A demultiplexer 904 selects one data line 902 at a time from the respective blocks, and the data signal is applied to the selected data line 902.
After the application of the data signal, a shift resistor 905 included in a testing circuit 906 sequentially outputs a shift signal Xi (i=1 to 120) to the corresponding blocks. The testing circuit 906 outputs, to read lines 907, the potentials of the four data lines 902 of the block to which the shift signal Xi was outputted. The test control circuit measures the potentials of the data lines 902 outputted to the read lines 907 to judge whether or not the selected data line 902 of the block to which the shift signal Xi was outputted is normal.
By performing this processing block-sequentially according to the shift signal Xi, and repeating the processing while selecting the other data lines 902 in the block, all the data lines 902 are tested.